• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a circuit comprising: a gate C having first and second input nodes and first and second inverters (110, 112) cross-coupled between first and second complementary storage nodes (Q, Z), the second storage node (Z) forming an output node of the gate C; and a nonvolatile memory comprising: a first resistive element (202) having a first terminal coupled to the first storage node (Q); a second resistive element (204) having a first terminal coupled to the second storage node (Z), at least one of the first and second resistive elements being programmable to take one of at least two resistive states (Rmin, Rmax ), a data value being represented by the relative resistances of the first and second resistive elements, a second terminal of the first resistive element (202) being coupled to a second terminal of the second resistive element (204) via a first transistor (210); and a control circuit (232) adapted, during a backup phase of a data bit stored at the first and second storage nodes in the non-volatile memory, to turn on the first transistor (210) while Different logical levels are applied to the first and second input nodes of the C-gate.
    公开号:FR3025674A1
    申请号:FR1458289
    申请日:2014-09-04
    公开日:2016-03-11
    发明作者:Pendina Gregory Di；Edith Beigne；Eldar Zianbetov
    申请人:Centre National de la Recherche Scientifique CNRS；Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] The present description relates to the field of asynchronous circuits, and in particular a gate C comprising a non-volatile memory for data backup.
    [0002] DESCRIPTION OF THE PRIOR ART Contrary to synchronous circuit designs which rely on a clock signal, the asynchronous circuits have the advantage of being more or less insensitive to delay variations resulting for example from variations in the manufacturing process. In addition, by avoiding the use of a clock, the asynchronous circuits have a relatively low energy consignation. Asynchronous circuits are generally designed to operate on the basis of determined events using a specific handshake protocol. The basic elementary circuit of an asynchronous design is based on a circuit known as the C gate or Muller circuit. This circuit includes a volatile flip-flop for storing a state. Thus, if the power of the asynchronous circuit is cut off, the data stored by the various doors C will be lost.
    [0003] It would be desirable to have a gate C having a nonvolatile storage capacity so that the state of the circuit can be restored following a power failure. However, there are technical problems in obtaining a solution in a compact circuit that does not lead to a significant increase in energy consumption. SUMMARY An object of embodiments of the present disclosure is to at least partially solve one or more problems of the prior art. In one aspect, there is provided a circuit comprising: a gate C having first and second input nodes and first and second inverters cross-coupled between first and second complementary storage nodes, the second storage node forming a exit node of the gate C; and a nonvolatile memory comprising: a first resistive element having a first terminal coupled to the first storage node; a second resistive element having a first terminal coupled to the second storage node, at least one of the first and second resistive elements being programmable to take one of at least two resistive states, a data value being represented by the relative resistors of the first and second resistive elements, a second terminal of the first resistive element being coupled to a second terminal of the second resistive element through a first transistor; and a control circuit adapted, during a backup phase to the nonvolatile memory of a data bit stored at the first and second storage nodes, to turn on the first transistor while different logic levels are applied to the first and second input nodes of the gate C. According to one embodiment, the first transistor is adapted to conduct a write current during the backup phase, and the circuit is arranged such that the current 3025674 B13471EN The writing device passes through at least one transistor of each of the first and second inverters during the write phase. According to one embodiment, the gate C is adapted to receive a first input signal on the first input node 5 and a second input signal on the second input node; and the first inverter comprises: first and second transistors having their control nodes coupled to the first or second storage node; third and fourth transistors coupled in parallel with each other and coupling the first transistor of the first inverter to a supply voltage rail; and fifth and sixth transistors coupled in parallel with each other and coupling the first transistor of the first inverter to the ground voltage rail. According to one embodiment, the second inverter 15 comprises: first and second transistors having their control nodes coupled to the second or the first storage node; and a third transistor coupling the first transistor of the second inverter to the supply voltage rail and having its control node coupled to the ground voltage rail.
    [0004] According to one embodiment, the fifth and sixth transistors of the first inverter and the second transistor of the second inverter are coupled to a common node, the circuit further comprising a seventh transistor coupled between the common node and the ground voltage rail.
    [0005] According to one embodiment, the circuit further comprises an eighth transistor coupled between the first resistive element and the ground voltage rail and a ninth transistor coupled between the second resistive element and the ground voltage rail, the control circuit. being further adapted to make 30 conductors the eighth and ninth transistors during a restoration phase of the data bit stored by the resistive elements to the storage nodes. According to one embodiment, the eighth transistor is coupled to the second terminal of the first resistive element, and the ninth transistor is coupled to the second terminal of the second resistive element. According to one embodiment, at least one of the first and second resistive elements is of one of the following types: a spin transfer torque element having anisotropy in the plane; a spin transfer torque element having anisotropy perpendicular to the plane; a redox element; a ferroelectric element; and a phase change element.
    [0006] According to one embodiment, the first and second resistive elements each comprise a third terminal, and the eighth transistor is coupled to the third terminal of the first resistive element, and the ninth transistor is coupled to the third terminal of the second resistive element.
    [0007] According to one embodiment, the resistive element is of the magnetic tunnel junction type with spin-orbit torque. In another aspect, there is provided an integrated circuit comprising a plurality of asynchronous blocks each comprising the aforementioned circuit.
    [0008] In another aspect, there is provided a method of backing up data in a circuit comprising: a gate C having first and second input nodes and first and second inverters cross-coupled between first and second complementary storage nodes the second storage node forming an output node of the gate C; and a nonvolatile memory comprising: a first resistive element having a first terminal coupled to the first storage node; a second resistive element having a first terminal coupled to the second storage node, at least one of the first and second resistive elements being programmable to take one of at least two resistive states, a data value being represented by the relative resistors of the first and second elements, a second terminal of the first resistive element being coupled to a second terminal of the second resistive element via a first transistor, the method comprising: conducting the first resistive element; transistor while different logic levels are applied to the first and second input nodes of the gate C. Brief description of the drawings The above and other advantages will be apparent from the following detailed description of embodiments. , given by way of illustration and not limitation, making reference in the accompanying drawings in which: Figure 1 schematically illustrates an example of a C gate; FIG. 2 diagrammatically illustrates a circuit comprising a gate C and a non-volatile memory according to an exemplary embodiment of the present description; Fig. 3 is a timing chart showing exemplary signals in the circuit of Fig. 2 according to an exemplary embodiment; FIG. 4 illustrates a resistive element of the circuit of FIG. 2 in more detail according to an exemplary embodiment; Figure 5 illustrates a resistive element of the circuit of Figure 2 in more detail according to another embodiment; FIG. 6 schematically illustrates a circuit comprising a gate C and a non-volatile memory according to another embodiment of the present description; and FIG. 7 illustrates a resistive element of the circuit of FIG. 6 in more detail according to an exemplary embodiment. DETAILED DESCRIPTION In the following description, the term "connected" is used to refer to a direct connection between two elements, while the term "coupled" is used to refer to a connection that could be direct or could be via one or more intermediate elements such as resistors, capacitors or transistors.
    [0009] FIG. 1 illustrates an example of gate C 100, also known as Muller circuit. It comprises two data input nodes for receiving input signals A and B. Two transistors 102, 104, which are for example PMOS transistors, are coupled in series between a VDD supply voltage rail and a storage node 0 of the gate C. Two other transistors 106, 108, which are for example NMOS transistors, are coupled in series between the storage node 0 and a ground voltage rail. Transistors 104 and 106 have their control nodes coupled to the input node receiving signal A and transistors 102 and 108 have their control nodes coupled to the input node receiving signal B. Two inverters 110, 112 are coupled crosswise between the storage node Q and another storage node Z which constitutes the output node of the gate C. The inverter 112 has for example its input coupled to the storage node Z and its output coupled to the node of storage 0, and has its power supply terminals coupled to the supply voltage rails through other transistors. In particular, a high power supply terminal of the inverter 112 is coupled to the supply voltage VDD rail via each transistor of a pair 114, 116, which are, for example, parallel coupled PMOS transistors. between them. The low supply terminal of the inverter 112 is coupled to the ground voltage rail via each transistor of a pair of transistors 118, 120, which are, for example, NMOS transistors, coupled in parallel with each other. . Transistors 114 and 118 have their control nodes coupled to the input node for receiving signal A, and transistors 116 and 120 have their control nodes coupled to the other input node for receiving signal B In operation, the gate C has for example an operation defined by the following truth table: In this way, in other words, when the values of the input signals A and B are at the same logical level, the output Z is set to this logical level. When the values of the input signals A and B are at different logic levels with each other, the circuit 5 is in a waiting state in which the output Z remains unchanged, in other words the voltage state on the storage nodes 0 and Z is not changed. FIG. 2 illustrates a circuit 200 comprising gate C 100 of FIG. 1, to which a non-volatile memory has been added. The elements of the door C 100 have been referenced with the same references in FIG. 2, and will not be described again in detail. The circuit 200 of FIG. 2 comprises two resistive elements 202, 204, each of which can be programmed to assume one of a plurality of resistive states. The resistive elements 202 and 204 may be resistance switching elements of any type for which the resistance is programmable by the direction of a current passed through it. For example, as will be described in more detail below with reference to FIGS. 4 and 5, the resistance switching elements 202, 204 are spin transfer torque elements having anisotropy in the plane or perpendicular to the plane. As described in more detail in the publication entitled "Magnonic spin-transfer torque MRAM with low power, high speed, and error-free switching", N. Mojumder et al., IEDM Tech. Digest (2010), and in the publication entitled "Electric toggling of magnets", E. Tsymbal, Natural Materials Vol 11, January 2012. Alternatively, the resistive elements could be those used in resistive switching memories called RAM RedOx (RAM redox), which are for example described in more detail in the publication entitled "Redox-Based Resistive Switching Memories - Nanoionic Mechanisms, Prospects and Challenges", Rainer Waser et al., Advanced Materials 2009, 21, pages 2632 to 2663. In yet another example, the resistive elements could be those used in FeRAM (ferroelectric RAM) or in PCRAM (phase change RAM). Whatever the type of the resistive elements, a data bit is for example stored in a nonvolatile manner by putting one of the elements at a relatively high resistance (Rmax), and the other at a relatively low resistance (Rmin). In the example of Figure 2, the element 202 is programmed to have a resistor Rmax and the element 204 a resistor Rmin representing a value of the data bit, and CORE that is represented by the references Rmin and Rmax in parentheses, the opposite programming of the resistance values stores the opposite value of the data bit. Each of the resistance switching elements 202, 204, for example, has only two resistive states corresponding to the high and low resistors Rmax and Rmin, but the exact values of Rmin and Rmax may vary depending on conditions such as the manufacturing process. materials, temperature variations, etc. The non-volatile data bit represented by the resistive elements 202, 204 depends on which of the resistive elements 25 has the resistance Rmax or Rmin, in other words the relative resistances. The resistive elements 202, 204 are for example chosen such that Rmax is always significantly greater than Rmin, for example, greater by at least 20%. In general, the ratio between the resistance Rmax and the resistance Rmin is, for example, between 1.2 and 10,000. Rmin is for example of the order of at least 2 kilo-ohms, and Rmax is, for example, order of 6 kilo-ohms or more, although other values are possible. It will be clear to those skilled in the art that in some embodiments, instead of the resistive elements 202 being programmable both, only one is programmable. In such a case, the other resistive element has for example a fixed resistance at the intermediate level about halfway between Rmin and Rmax, for example equal, with a tolerance of 10%, to 5 (Rmin + (Rmax-Rmin) / 2). For example, one of the resistive elements 202, 204 could correspond to a fixed value resistor. Alternatively, one of the resistive elements 202, 204 could consist of a pair of programmable resistive elements coupled in parallel with each other with opposite orientations, so that whatever the direction in which each element is programmed, the resistance value remains relatively constant at the intermediate level. The resistive element 202 is coupled between the storage node 0 and an intermediate node 206. The resistive element 204 is coupled between the storage node Z and an intermediate node 208. The intermediate nodes 206 and 208 are coupled together by via a transistor 210, which is for example an NMOS transistor. The transistor 210 receives on its control node a write signal WR.
    [0010] The node 206 is further coupled to the ground voltage rail via a transistor 212, which is for example a PMOS transistor. Similarly, the node 208 is further coupled to the ground voltage rail via a transistor 214, which is also for example an NMOS transistor. The control nodes of the transistors 212 and 214 are controlled by a read signal RD. Figure 2 also illustrates the inverters 110 and 112 in more detail. The inverter 110 comprises, for example, a transistor 216, which is for example a PMOS transistor, coupled between the storage node Z and the supply voltage rail VDD. Optionally, for the purpose of balancing the read paths during a restoration phase described in more detail below, another transistor 217, which is for example a PMOS transistor, is coupled between the transistor 216 and the voltage rail 35. VDD power supply. The inverter 110 also includes, for example, a transistor 218, which is for example an NMOS transistor, coupled between the storage node Z and a common node 220. In some embodiments, the common node 220 is is connected to the ground voltage rail, whereas in alternative embodiments as shown in FIG. 2, the common node 220 is coupled to the ground voltage rail via a transistor 222, which is for example an NMOS transistor controlled by a signal Az described in detail below.
    [0011] The inverter 112 comprises, for example, a transistor 226, which is for example a PMOS transistor, coupled between the storage node Q and the high voltage terminal of the inverter 112. The inverter 112 also comprises, for example, a transistor 228. , which is for example an NMOS transistor, coupled between the storage node Q and the supply voltage terminal of the inverter 112. The transistors 118 and 120 are coupled between the low voltage terminal of the inverter 112 and common node 220. Optionally, a transistor 230, which is for example a PMOS transistor having its control node coupled to receive the signal Az, is coupled between the storage nodes Q and Z. FIG. control block 232, supplying the control signals RD, WR and Az to the corresponding transistors of the circuit 200.
    [0012] The operation of the circuit 200 of FIG. 2 will now be described with reference to the timing diagram of FIG. 3. The gate portion C of the circuit 200 is for example capable of normal operation, unaffected by the non-volatile circuit 30. while the RD and WR signals remain low, and the signal Az is high. A backup phase may be performed periodically or only before a power-down period, and involves storing the bit represented by the voltage states on the Q and Z storage nodes as a programmed resistive state of the resistor elements 202, 3025674 B13471bR - BD15495 - D107156 11 204. A restoration phase is for example carried out after the powering on, and involves putting the voltage states on the storage nodes 0 and Z according to the programmed resistive states of the resistive elements 202, 204.
    [0013] FIG. 3 illustrates examples of the voltage VDD on the supply voltage rail, signals A and B, the voltage on the storage node Z, the write signal WR, the read signal RD, the signal Az, of the current 1202 in the resistive element 202, the current 1204 in the resistive element 204, the resistor R202 of the resistive element 202 corresponding to its magnetic state, and the resistor R204 of the resistive element 204 corresponding to its magnetic state. A first period 302 in FIG. 3 corresponds to a standard operation, in which the signals A and B both go from a low state to a high state, and Z goes high for a period in which both signals A and B are high and at least one of the signals remains high. In a subsequent period 304, a zero state is set on the storage node Z by causing the two signals A and B to go low. Subsequent periods 306 and 308 correspond to a backup phase during which the zero state stored by the storage node Z is stored in the resistive elements 202, 204. This implies an initial step represented by the period 306 in which the one of the signals A and B is brought to the high state. This corresponds, for example, to a waiting state in which gate C is input. Thus, at least one of transistors 114, 116, and at least one of transistors 118, 120 will be conducting. In the example of FIG. 3, the signal A is brought to the high state. Then, during the period 308, the write signal WR is activated, which for example causes the passage of a positive current in the resistive element 202 and the passage of a negative current in the resistive element 204. In In particular, with reference to FIG. 2, an alternating line illustrates an example of the path of this write current, which passes from the VDD supply rail, through transistors 116 and 226, by the resistive element 202, by the transistor 210, by the resistive element 204 and by the transistors 218 and 222, towards the ground rail. Advantageously, the generation of the write current thus makes use of the existing transistors of the gate C. The write signal WR then goes back to the low state, and a power-off period 310 takes place while the voltage VDD on the supply voltage rail is brought to the low state. Although the duration of this period is relatively short in the example of FIG. 2, it may be of any duration. The signal Az, which is normally high, also goes low for example during the power-off period 310. At the end of the power-off period 310, the voltage VDD and the signal Az are again brought to the high state, and the gate C goes into an unpredictable state, this being in the example of Figure 3 the zero state. The signals A and B are then both enabled to set the state to logical state 1, although this step is optional, and here only serves to illustrate that a restoration is possible regardless of the initial state of the state. gate C. In a following period 312, a restoration phase takes place in which the signal Az is brought to the low state. This has the effect of bringing the voltage on the memory nodes to an intermediate level. In addition, the signal RD is raised to make conductive the transistors 212 and 214, and generate currents in each of the resistive elements 202, 204. The current level in each resistive element 202, 204 will depend on its programmed resistance. Then, when the signal Az is again raised to high, the unbalanced current in each branch causes the voltage on the storage node Z to go to a low value. The signal RD then goes low to make the transistors 212 and 214 non-conductive.
    [0014] For subsequent periods 316 to 326, the same operations take place as during periods 304 to 312, except that a logic state 1 is programmed on the storage node Z instead of the state. zero. Note that in period 318, one of the signals A and B is brought low to ensure that at least one of transistors 114, 116 and at least one of transistors 118, 120 is driver. As shown by a dotted arrow in FIG. 2, the write current during the period 320 will flow from the supply rail VDD, through the transistors 217 and 216, through the resistive element 204, by the transistor 210, by the resistive element 202 and by the transistors 120 and 122, to the ground rail. Figures 4 and 5 illustrate the structures of spin transfer torque (STT) elements according to exemplary embodiments. For example, each of the resistive elements 202 and / or 204 of FIG. 2 has a structure corresponding to that of FIG. 4 or FIG. 5. Alternatively, as mentioned previously, the resistive elements could be elements of FIG. RAM redOx, FeRAM elements, PCRAM elements, or other types of resistive elements having programmable current resistance. FIG. 4 illustrates an STT resistive element 400 having a magnetic anisotropy in the plane. The element 400 is for example substantially cylindrical, but has a section that is non-circular, for example oval, which leads for example to an increase in the retention stability of the resistive states when the device is programmed. Element 400 comprises lower and upper electrodes 402 and 404, each substantially disk-shaped, and sandwiching therebetween a number of intermediate layers. The intermediate layers comprise, from bottom to top, a fixed layer 406, an oxidation barrier 408, and a storage layer 410. The oxidation barrier 408 is for example made of MgO or AlxOy. The fixed layer 406 and the storage layer 410 are for example made of ferromagnetic material, such as CoFe. The spin direction of the fixed layer 406 is fixed, as shown by an arrow from left to right in FIG. 4. Of course, in alternative embodiments, the spin direction could be from the right towards the left in the fixed layer 406. However, the spin direction in the storage layer 410 can be changed, as shown by arrows in opposite directions in FIG. 4. The spin direction is programmed by the direction of the current 10 in the element, so that the spin direction in the storage layer is parallel, in other words in the same direction, or antiparallel, in other words in the opposite direction to that of the fixed layer 406.
    [0015] Figure 5 illustrates an STT resistive element 500 having a magnetic anisotropy perpendicular to the plane. Such a resistive element may for example be programmed by a writing current I less than that of the element 400 for a given size and / or for a given storage layer volume.
    [0016] The element 500 is substantially cylindrical, and has for example a section which is circular. Element 500 comprises lower and upper electrodes, 502 and 504, each substantially disk-shaped and sandwiching a number of intermediate layers. The intermediate layers 25 comprise, from bottom to top, a fixed layer 506, an oxidation barrier 508, and a storage layer 510. These layers are similar to the corresponding layers 406, 408 and 410 of the element 400, except that the fixed layer 506 and the storage layer 510 have anisotropy perpendicular to the plane, as represented by the vertical arrows in the layers 506 and 510 of FIG. 5. The fixed layer 506 is illustrated as having a direction of spin from bottom to top in Figure 5, but of course, in alternative embodiments, this direction of spin could be from top to bottom.
    [0017] If the STT element 400 or 500 of FIG. 4 or 5 is used to implement each of the resistive elements 202, 204 described here, their orientations may for example be chosen to minimize the current level. writing which makes it possible to program them. In particular, depending on factors such as the dimensions of the elements 202, 204, a low write current could be possible when each element has its lower electrode 402, 502 connected to the corresponding storage node Q, Z, or vice versa. be true.
    [0018] FIG. 6 schematically illustrates a circuit 600 according to an alternative embodiment very similar to the circuit of FIG. 2, and the same elements bear identical references and will not be described again in detail. However, in the embodiment of FIG. 6, the resistive elements 202, 204 have been replaced by resistive elements 602, 604 respectively, each of them being a three-terminal device, as will now be described by reference. FIG. 7 illustrates, in a perspective view, the resistive element 602 of FIG. 6 in more detail according to an exemplary embodiment. The resistive element 604 for example has a similar structure. The resistive element 602 is, for example, a magnetic tunnel with a spin-orbit torque (SOT-MTJ). Such a device is, for example, described in more detail in Voltage and Energy-Delay Performance of Giant Spin Hall Effect Switching for Magnetic Memory and Logic, S. Manipatruni et al., And in the publication Spin- Torque Switching with the Spin Giant Spin Hall of Tantalum ", Lugiao Liu et al., DOI: 10.1126 / Science.1218197 Science 336, 555 (2012), the contents of which form part of the present disclosure within the limits permitted by law . The resistive memory element 602 comprises three connection terminals, referenced a, b and c in FIG. 7. The terminal c is part of a resistive stack 702 which comprises an electrode 704 formed on a nano-magnetic reference layer 706 The layer 706 itself is made of an insulating layer 708, and the layer 708 itself is formed on a non-magnetic storage layer 710. The reference layer 706 corresponds to a layer 708. magnetic in which the direction of magnetization is fixed. The storage layer 710 on the contrary corresponds to a magnetic layer in which the direction of magnetization can be controlled. The resistive stack 702 is formed on a conductive layer 712 which provides the interface for programming the magnetization direction of the storage layer 710. The conductive layer 712 consists for example of: tantalum p ((3-Ta) tungsten p (13-W) and / or platinum (Pt), and comprises, for example, at opposite ends, an electrode 714 forming a terminal a of the element 700 and an electrode 716 forming a terminal b of the element 700. Each of the electrodes 714, 716 is for example made of copper, or of another suitable material As represented by arrows Ba in FIG. 7, a static magnetic field, provided for example by a For example, a permanent magnet or a polarization layer is present near the reference layer 706. Such a magnetic field is for example described in more detail in the publication entitled "Perpendicular switching of a single ferromagnetic layer induced by in-pl The present invention is incorporated herein by reference, and is incorporated herein by reference, and is incorporated herein by reference. During a write operation, a current is applied from terminal a to terminal b, or in the opposite direction, to program the magnetization direction in storage layer 710. As shown by FIG. arrows x, y, and z in FIG. 7, the direction of the write current Iw passing in conductive layer 712 from terminal a to terminal b will be called direction + x, direction 35 perpendicular to direction + x in the plane of the conductive layer will be called the + y direction, and the upward direction perpendicular to the directions + x and + y will be referred to as + z direction. A positive write current Iw in the + x direction will produce a spin injection current with a transport direction in the + z direction, and spins pointing in the + y direction. The spin current injected in the + z direction will in turn produce a spin couple to align the magnetization in the + y direction. A negative write current Iw in the -x direction will produce a spin injection current with a transport direction in the -z direction, and spins pointing in the -y direction. The spin current injected in the -z direction will in turn produce a spin torque to align the magnetization in the -y direction. When the magnetization direction in the storage layer 710 is the same as that of the reference layer 706, the resistance of the resistive stack 702 is, for example, at a relatively low value Rmin- When the direction of the magnetization in the storage layer 710 is opposite to that of the reference layer 706, the resistance of the resistive stack 702 is, for example, at a relatively high value Rmax. It will be apparent to those skilled in the art that the structure represented in FIG. 7 is only one example of a possible structure of a three-terminal programmable resistive element. In alternative embodiments, one or more additional layers could be included, and different combinations of materials could be used. Furthermore, it will be apparent to those skilled in the art that an additional reading node could be provided, for example on the underside of the conductive layer 712, or elsewhere, so that the electrodes 714 and 716 would be used. exclusively for writing. The operation of the circuit of FIG. 6 is very similar to that of FIG. 2, and will not be described in detail. An advantage of the embodiments described herein is that by performing a backup phase during a waiting phase of the C-gate during which the signals A and B have different logic levels, the transistors already present in the gate C may be used to pass the write current for programming the resistive states of the resistive elements. With the description thus made of at least one illustrative embodiment, various alterations, modifications and improvements will readily occur to those skilled in the art. For example, it will be apparent to those skilled in the art that the supply voltage V DD in the various embodiments could have any level, for example, between 1 and 3 V, and rather than being at 0V, the ground voltage could also be considered as a supply voltage which could have any level, such as a negative level. In addition, it will be apparent to those skilled in the art that in all the embodiments described herein, all NMOS transistors could be replaced by PMOS transistors and / or all PMOS transistors could be replaced by transistors. NMOS. The way in which the circuits could be implemented using only PMOS transistors or only NMOS transistors will be clear to those skilled in the art, for example by reversing the supply rails. In addition, although transistors based on MOS technology have been described here, in alternative embodiments other transistor technologies, such as bipolar technology, could be used. In addition, it will be apparent to those skilled in the art that the various elements described in connection with the various embodiments may be combined in alternative embodiments, in any combination.
    权利要求:
    Claims (12)
    [0001]
    REVENDICATIONS1. A circuit comprising: a gate C having first and second input nodes and first and second inverters (110, 112) cross-coupled between first and second complementary storage nodes (O, Z), the second storage node (Z) forming an output node of the gate C; and a non-volatile memory comprising: a first resistive element (202, 602) having a first terminal coupled to the first storage node (0); a second resistive element (204, 604) having a first terminal coupled to the second storage node (Z), at least one of the first and second resistive elements being programmable to take one of at least two resistive states (Rmin , Rmax), a data value being represented by the relative resistances of the first and second resistive elements, a second terminal of the first resistive element (202, 602) being coupled to a second terminal of the second resistive element (204, 604) by via a first transistor (210); and a control circuit (232) adapted, during a backup phase to the nonvolatile memory of a stored data bit at the first and second storage nodes, to turn on the first transistor (210) while Different logical levels are applied to the first and second input nodes of the C-gate.
    [0002]
    2. Circuit according to claim 1, wherein the first transistor (210) is adapted to conduct a write current during the backup phase, and wherein the circuit is arranged so that the write current passes through. at least one transistor of each of the first and second inverters (110, 112) during the write phase.
    [0003]
    The circuit of claim 1 or 2 wherein: the gate C is adapted to receive a first input signal (A) on the first input node and a second input signal (B) on the second node 'Entrance ; and the first inverter (112) comprises: first and second transistors (226, 228) having their control nodes coupled to the first or second storage nodes (Q, Z); third and fourth transistors (114, 116) coupled in parallel with each other and coupling the first transistor of the first inverter to a supply voltage (VDD) rail; and fifth and sixth transistors (118, 120) coupled in parallel with each other and coupling the first transistor of the first inverter to the ground voltage rail. 10
    [0004]
    The circuit of any one of claims 1 to 3, wherein the second inverter (110) comprises: first and second transistors (216, 218) having their control nodes coupled to the second or the first storage node; and a third transistor (217) coupling the first transistor of the second inverter to the supply voltage rail and having its control node coupled to the ground voltage rail.
    [0005]
    The circuit of any one of claims 1 to 4, wherein the fifth and sixth transistors of the first inverter (112) and the second transistor of the second inverter are coupled to a common node (220), the circuit further comprising a seventh transistor (222) coupled between the common node and the ground voltage rail.
    [0006]
    The circuit of any one of claims 1 to 5, further comprising an eighth transistor (212) coupled between the first resistive element (202, 602) and the ground voltage rail and a ninth coupled transistor (214). between the second resistive element (204, 604) and the ground voltage rail, the control circuit (232) being further adapted to conduct the eighth and ninth transistors (212, 214) during a bit recovery phase. of data stored by the resistive elements to the storage nodes (Q, Z).
    [0007]
    The circuit of claim 6, wherein the eighth transistor (212) is coupled to the second terminal of the first resistive element (202), and the ninth transistor (214) is coupled to the second terminal of the second resistive element (204). ). 3025674 B13471EN - BD15495 - DI07156 21
    [0008]
    The circuit of any one of claims 1 to 7, wherein at least one of the first and second resistive elements (202, 204) is of one of the following types: a spin transfer torque element having anisotropy in the plane; a spin transfer torque element having anisotropy perpendicular to the plane; a redox element (RedOx); a ferroelectric element; and a phase change element.
    [0009]
    The circuit of claim 6, wherein the first and second resistive elements (602 604) each comprise a third terminal, and wherein the eighth transistor (212) is coupled to the third terminal of the first resistive element (602), and the ninth transistor (214) is coupled to the third terminal of the second resistive element (604).
    [0010]
    The circuit of claim 9, wherein the resistive element is of the spin-orbit torque magnetic tunnel junction type (SOT-MTJ). 20
    [0011]
    An integrated circuit comprising a plurality of asynchronous blocks each comprising the circuit of any one of claims 1 to 10.
    [0012]
    A method of saving data in a circuit comprising: a gate C having first and second input nodes and first and second inverters (110, 112) cross-coupled between complementary first and second storage nodes (Q); , Z), the second storage node (Z) forming an output node of the gate C; and a non-volatile memory comprising: a first resistive element (202, 602) having a first terminal coupled to the first storage node (Q); a second resistive element (204, 604) having a first terminal coupled to the second storage node (Z), at least one of the first and second resistive elements being programmable to take one of at least two resistive states (Rmin , Rmax), a data value being represented by the relative resistances of the first and second elements, a second terminal of the first resistive element being coupled to a second terminal of the second resistive element via a first transistor (210), the method comprising: rendering the first transistor (210) conductive while different logic levels are applied to the first and second input nodes of the C-gate.
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    同族专利:
    公开号 | 公开日
    EP2993786B1|2016-09-21|
    FR3025674B1|2016-09-09|
    US9412448B2|2016-08-09|
    EP2993786A1|2016-03-09|
    US20160071587A1|2016-03-10|
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    RU2733263C1|2020-03-06|2020-10-01|Федеральное государственное учреждение "Федеральный исследовательский центр "Информатика и управление" Российской академии наук" |Device of fault-tolerant discharge of self-synchronized storage register|
    法律状态:
    2015-09-22| PLFP| Fee payment|Year of fee payment: 2 |
    2016-03-11| PLSC| Publication of the preliminary search report|Effective date: 20160311 |
    2016-09-28| PLFP| Fee payment|Year of fee payment: 3 |
    2018-06-29| ST| Notification of lapse|Effective date: 20180531 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1458289A|FR3025674B1|2014-09-04|2014-09-04|DOOR C WITH NON-VOLATILE BACKUP|FR1458289A| FR3025674B1|2014-09-04|2014-09-04|DOOR C WITH NON-VOLATILE BACKUP|
    EP15183551.9A| EP2993786B1|2014-09-04|2015-09-02|C-element having non-volatile storage|
    US14/845,213| US9412448B2|2014-09-04|2015-09-03|C-element with non-volatile back-up|
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